1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly, a nonvolatile memory which can be electrically rewritten, for example, a semiconductor nonvolatile memory device such as a flash EEPROM.
2. Description of the Related Art
As a symmetrical arrangement of a bit line and an inverted bit line having a complementary level to this in a semiconductor memory device, for example, a dynamic random access memory (DRAM) circuit, there is a so-called differential type sensing circuit (including flip-flop type), wherein, to produce a reference level for a differential sense amplifier, a reference cell referred to as a dummy cell corresponding to a storage cell is arranged in the inverted bit line on the opposite side to the side for reading data.
Conventionally, it has been impossible for a flash EEPROM, particularly a NAND type, to adopt the so-called folded bit line method which is advantageous for the enhancement of speed etc. and has been adopted in a DRAM circuit etc.
Therefore, as shown in FIG. 1, there has been adopted an open bit line system (refer to for example Document 1: "A Quick Intelligent Program Architecture for 3V-only NAND EEPROMS"; Sympo. VLSI Cir. pp 20-21. 1992) in which data lines DLR and DLL which become symmetrical lines around a sense amplifier (SA) 1 are separated in terms of position, and memory cell arrays (MCAR) 11 and (MCAL) 6 are connected as the storage cells and dummy cells (DCLR) 14 and (DCLL) 2 to the respective data lines (DR) 2 and (DL) 15.
In the above-mentioned open bit line system, however, even though lines are in a symmetrical arrangement, they are separated in terms of position, and therefore there is liable to be an imbalance in the electrical characteristics between the symmetrical lines. Further, it is not possible to completely equalize the noise voltage resulting from connection from another conductive body such as a peripheral circuit to the symmetrical lines. Therefore, the influence of the noise is larger than that of the folded bit line system and it is difficult to achieve an enhancement of sensitivity of the sense amplifier, resulting in a problem that the enhancement of speed was difficult.
As a result, a NAND type cell has been considered as a low speed and large capacity memory, and the random access time becomes about 1 .mu.s.
Also, as shown in FIG. 2, to construct the folded bit line system, a divided bit line system having a divided bit line structure (document 2: "High Speed Page Mode Sensing Scheme for EPROM's and Flash EEPROM's using Divided Bit Line Architecture"; SympoVLSI Cir. pp 97-98, 1990) has been proposed.
Note that, in FIG. 2, SA denotes a sense amplifier 44; SRG denotes a storage cell 35; DCL denotes a dummy cell 25; WL denotes a word line 33; DWL denotes a dummy word line 23; BL denotes a bit line 21; BL.sub.-- denotes an inverted bit line 22; nt.sub.1 to nt.sub.4 denote n-channel MOS transistors 30, 27, 39, 41; and C.sub.B denotes a capacitor 26, 29, 37, 38; respectively. The folded bit line system is realized by dividing the bit line by turning on and off the transistors (nt.sub.1 to nt.sub.4) 30, 32, 39, 41 by the signals (SW1) 31 and (SW2) 40.
In this divided bit line system, however, due to the necessity of sensing by connecting the divided bit line, the potential difference between the bit line BL and inverted bit line BL.sub.-- which were especially provided is reduced to a half potential difference. This disadvantage will be explained in further detail below referring to FIG. 2.
Now assume that the signals (SW1) 31 and (SW2) 40 are at the low level, the transistors (nt.sub.1 to nt.sub.4) 30, 27, 39, are in the OFF state, the storage cell (SRG) 35 and dummy cell (EMIL) 25 pass a current, and the potentials of the bit line (BL) 21 or the inverted bit line (BL.sub.--) 22 become as follows:
VBL1=0 V PA1 VBL2=VPC--AVBL2 PA1 VBL1=VPC--AVBL1 PA1 VBL2=0V
where, VPC indicates a precharge level.
Here, when assuming that the signal (SW1) 31 is made the high level and the transistors (nt.sub.1 and nt.sub.3) 30 and 39 are brought to the ON state, the following formulas stand: EQU VBL=(1/2) (VBL1+VBL2)=(1/2) (VPC-.DELTA.VBL2) (1) EQU VBL.sub.-- =(1/2) (VBL1.sub.-- +VBL2.sub.--)=(1/2) (VPC-.DELTA.VBL1.sub.--) (2)
Accordingly, it becomes: EQU .DELTA.VBL--BL.sub.-- =VBL--VBL.sub.-- =(1/2) (.DELTA.VBL1.sub.-- -.DELTA.VBL2) (3)
In this way, it becomes the potential difference of 1/2.